Monza, Italy

Giovanna Dalla Libera

This inventor holds 34 USPTO granted patents and 1 EPO patent, primarily in Non-Volatile Memory. Top assignees: Stmicroelectronics S.r.l., Sgs-Thomson Microelectronics S.r.l., Sgs-Thomson Microelectronics Limited. Active years: 1999-2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Giovanna Dalla Libera. Retrieved from https://idiyas.com/inventor/giovanna-dalla-libera

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0


Average Co-Inventor Count = 3.4

ph-index = 6

Forward Citations = 177(Granted Patents)


Company Filing History:


Years Active: 1999-2003

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Areas of Expertise:
Non-Volatile Memory
EEPROM Devices
Memory Cell Fabrication
CMOS Process
High-Voltage Transistors
Salicided Junctions
Multi-Level ROM
Dimensional Control
Mass-Storage Memory
Floating Gate Regions
Transistor Manufacturing
Threshold Voltage Adjustment
34 patents (USPTO):Explore Patents

Title: Giovanna Dalla Libera: Pioneering Innovations in Semiconductor Technology

Introduction

Giovanna Dalla Libera is an accomplished inventor based in Monza, Italy, with a remarkable portfolio of 34 patents. Her innovative work is primarily focused on circuit structures and the manufacturing methods of electronic devices, specifically in semiconductor technology.

Latest Patents

Among her latest contributions to the field are two notable patents. The first, titled "Circuit structure with a parasitic transistor having high threshold voltage," outlines a circuit structure integrated in a semiconductor substrate. This design includes at least one pair of transistors, each formed in a respective active area. These transistors feature a source region and a drain region, as well as a channel region intervening between the two. A key aspect of this invention is the gate region, which is electrically connected through an overlying conductive layer, with contacts established between the gate regions and the conductive layer above the active areas.

The second patent, "Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions," describes a comprehensive manufacturing method. This method meticulously details the sequential steps of depositing an upper layer of polycrystalline silicon, defining the upper layer to obtain low-voltage (LV) gate regions and source and drain regions, and forming a layer of silicide. Furthermore, it elaborates on defining stack gate regions and high-voltage (HV) gate regions of transistors, ensuring the efficiency of electronic devices.

Career Highlights

Throughout her career, Dalla Libera has made significant contributions while working for leading companies in the semiconductor industry, including STMicroelectronics S.r.l. and SGS-Thomson Microelectronics S.r.l. Her expertise has played a critical role in advancing the technology used in electronic devices.

Collaborations

Giovanna has collaborated with notable professionals in her field, including her coworkers Bruno Vajana and Matteo Patelmo. These partnerships have fostered a rich exchange of ideas, driving innovation and contributing to the successful development of advanced semiconductor technologies.

Conclusion

Giovanna Dalla Libera's impressive patent portfolio and her dedication to innovation in the semiconductor industry exemplify her role as a leading inventor. Her contributions are instrumental in advancing electronic device manufacturing and circuit design, reflecting the importance of female inventors in a predominantly male-dominated field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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