Simplified dscp process for manufacturing flotox eeprom non-autoaligned semiconductor memory cells

Abstract

A simplified DSCP process makes non-self-aligned floating gate semiconductor memory cells of the FLOTOX EEPROM type as incorporated to a cell matrix having control circuitry associated therewith, wherein each cell has a selection transistor associated therewith. The process includes at least the following steps: growing or depositing a gate dielectric layer of the selection transistor and the cell; tunnel masking to define the tunnel area with a dedicated etching step for cleaning the semiconductor surface; growing the tunnel oxide; depositing and doping the first polysilicon layer poly1. The process further comprises the following steps: poly1 masking to fully define the floating gate of the cell, the poly1 being removed from the area of the selection transistor during this step; depositing or growing the interpoly dielectric and forming tunnel oxide and interpoly dielectric; depositing or growing the interpoly dielectric and forming the overall gate dielectric of the selection transistor, which will therefore consist of the stacked interpoly dielectric and gate dielectric as previously grown or deposited; matrix masking to only remove interpoly dielectric from the circuitry; depositing and doping a second polysilicon layer poly2; masking the second layer of polysilicon to define the control and selection gate; poly etching in the matrix as far down as the intermediate dielectric layer; poly etching in the circuitry the whole short-circuited poly1/poly2 stack.