Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Sgs-thomson Microelectronics Limited

Giovanna Dalla Libera

Bruno Vajana

Matteo Patelmo

Nadia Galbiati

Carlo Cremonesi

Roberta Bottini

Federico Pio

A circuit structure integrated in a semiconductor substrate comprises at least one pair of transistors each being formed each in a respective active area region and having a source region and a drain region, as well as a channel region intervening between the source and drain regions and being overlaid by a gate region. The gate regions are connected electrically together by an overlying conductive layer and respective contacts. The contacts between the gate regions and the conductive layer are formed above the active areas.

Circuit structure with a parasitic transistor having high threshold voltage

The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a layer of silicide on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining stack gate regions and HV gate regions of high-voltage transistors; and forming HV source and drain regions and cell regions.

Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions

Presented is a method for obtaining a multi-level ROM in a dual gate EEPROM process flow. The method begins with, on a semiconductor substrate, defining active areas respectively for transistors of ROM cells, transistors of electrically erasable non-volatile memory cells, and additional transistors of the storage circuitry. Then, integrated capacitors are integrated in the storage circuit. According to this method, during the implanting step for forming integrated capacitors, at least an active area of the ROM cell is similarly implanted.

Method for obtaining a multi-level ROM in an EEPROM process flow

A process that provides for the manufacture of LV transistors with salicidated junctions on first areas of a substrate, HV transistors on second areas, and memory cells on third areas. The process includes forming LV oxide regions and LV gate regions on the first areas, HV oxide regions on the second areas, selection oxide regions, tunnel oxide regions, and matrix oxide regions on the third areas; forming floating gate regions and insulating regions on the tunnel oxide regions and the matrix oxide regions; forming first LV source and drain regions laterally to the LV gate regions; forming silicide regions on the first source and drain regions and on the LV gate regions; forming semiconductor material regions completely covering the second and third areas; and at the same time forming HV gate regions on the HV oxide regions, forming selection gate regions on the selection oxide regions, and forming control gate regions on the insulating regions through shaping of the semiconductor material regions.

Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors

A semiconductor memory device having at least one memory cell row, each memory cell having an information storing element and a related select transistor for selecting the storing element. The select transistor includes a gate oxide region over a silicon substrate, a lower polysilicon layer and an upper polysilicon layer superimposed to the gate oxide region and electrically insulated by an intermediate dielectric layer interposed therebetween. The gate oxide regions of the select transistors of the at least one row are separated by field oxide regions, and the lower and upper polysilicon layers and the intermediate dielectric layer extend along the row over the gate oxide regions of the select transistors and over the field oxide regions. Along the row there is at least one opening in the upper polysilicon layer, intermediate dielectric layer and lower polysilicon layer, inside of which a first contact element suitable to electrically connect the lower and upper polysilicon layers is inserted.

Low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process

A process for manufacturing a semiconductor memory device includes double polysilicon level non-volatile memory cells and shielded single polysilicon level non-volatile memory cells in the same semiconductor material chip. A first memory cell includes a MOS transistor having a first gate electrode and a second gate electrode superimposed and respectively formed by definition in a first and a second layer of conductive material. A second memory cell is shielded by a layer of shielding material for preventing the information stored in the second memory cell from being accessible from the outside. The second memory cell includes a MOS transistor with a floating gate electrode formed simultaneously with the first gate electrode of the first cell by definition of the first layer of conductive material. The layer of shielding material is formed by definition of the second layer of conductive material.

Process for producing a semiconductor memory device comprising mass-storage memory cells and shielded memory cells for storing reserved information

The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type. Specifically, some of the transistors of the ROM cells have their polysilicon layers masked and the ROM cells are then implanted by a first dopant species in the active areas of the exposed transistors. Then the masks are removed from the polysilicon layer, and a second dopant species is implanted in said previously covered layer.

Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell

A simplified DSCP process makes non-self-aligned floating gate semiconductor memory cells of the FLOTOX EEPROM type as incorporated to a cell matrix having control circuitry associated therewith, wherein each cell has a selection transistor associated therewith. The process includes at least the following steps: growing or depositing a gate dielectric layer of the selection transistor and the cell; tunnel masking to define the tunnel area with a dedicated etching step for cleaning the semiconductor surface; growing the tunnel oxide; depositing and doping the first polysilicon layer poly1. The process further comprises the following steps: poly1 masking to fully define the floating gate of the cell, the poly1 being removed from the area of the selection transistor during this step; depositing or growing the interpoly dielectric and forming tunnel oxide and interpoly dielectric; depositing or growing the interpoly dielectric and forming the overall gate dielectric of the selection transistor, which will therefore consist of the stacked interpoly dielectric and gate dielectric as previously grown or deposited; matrix masking to only remove interpoly dielectric from the circuitry; depositing and doping a second polysilicon layer poly2; masking the second layer of polysilicon to define the control and selection gate; poly etching in the matrix as far down as the intermediate dielectric layer; poly etching in the circuitry the whole short-circuited poly1/poly2 stack.

Simplified DSCP process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cells

A simplified non-DSCP process for the definition of the tunnel area in nonvolatile memory cells with semi-conductor floating gates is presented. The memory cells are non-aligned and are incorporated in a matrix of cells and have associated control circuitry. In additional, to each cell a selection transistor is associated. The process includes at least the following phases: growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells; tunnel mask for defining the area of tunnel; cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semiconductor; and growth of tunnel oxide. Advantageously, the tunnel mask is extended above the region occupied by the selection transistor.

Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells

A process for manufacturing a programmable non-volatile memory device having floating-gate MOS transistors, and first and second MOSFETs, the second MOSFETs capable of sustaining gate voltages higher than the first MOSFETs, by forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the first MOSFETs, and a third gate oxide layer for the second MOSFETs. The process includes: forming a first oxide layer over a substrate; selectively removing the first oxide layer from surface regions over the first MOSFETs, but not from surface regions over the floating-gate MOS transistors or the second MOSFETs; forming a second oxide layer over the first oxide layer and the regions over the first MOSFETs; removing the first and second oxide layer from a tunnel oxide region of the floating-gate MOS transistors; and forming a tunnel oxide layer over the second oxide layer and tunnel region oxide layer.

Process for the manufacturing of an electrically programmable non-volatile memory device

A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.

Memory cell for EEPROM devices, and corresponding fabricating process

A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining salicided HV gate regions of high voltage transistors; and forming HV source and drain regions not directly overlaid by silicide portions.

Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions

To increase the facing surface and thus the coupling between the floating gate and control gate regions of a memory cell, the floating gate and control gate regions have a width that is not constant in different section planes parallel to a longitudinal section plane extending through the source and drain regions of the cell. In particular, the width of the floating gate and control gate regions is smallest in the longitudinal section plane and increases linearly in successive parallel section planes moving away from the longitudinal section plane.

High efficiency memory device

A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.

Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions

A manufacturing process including: forming a substrate and insulating layer including a tunnel area; and simultaneously forming a floating gate region of a memory transistor and a lower gate portion of a selection transistor, the floating gate region internally forming a hole, one side of which delimits, together with an external side of the floating gate region, a portion of tunnel arranged above the tunnel area; a dielectric material layer is then deposited, and fills the hole of the floating gate region; the structure is planarized by CMP, and an insulating region of dielectric material is formed; and a control gate region is formed above the floating gate region and simultaneously an upper gate portion is formed above the lower gate portion. The upper and lower gate portions form a control gate region of the selection transistor. In this way, the upper gate portion and the control gate region are substantially on the same level.

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Monza, Italy

Giovanna Dalla Libera