Montreal, Canada

Geoffrey D Duerden

This inventor holds 2 USPTO granted patents. Top assignee: Dft Microsystems, Inc.. Active years: 2007-2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Geoffrey D Duerden. Retrieved from https://idiyas.com/inventor/geoffrey-d-duerden

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 4.2

ph-index = 2

Forward Citations = 15(Granted Patents)


Company Filing History:


Years Active: 2007-2008

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2 patents (USPTO):Explore Patents

Title: **Innovations of Geoffrey D Duerden: A Pioneer in Circuit Testing Technology**

Introduction

Geoffrey D Duerden is an inventive mind located in Montreal, Canada, known for his remarkable contributions to circuit testing technologies. With a portfolio of two patents, Duerden has made significant strides in developing systems and methods that enhance the efficiency and quality of electronic testing.

Latest Patents

Duerden's latest innovations include two remarkable patents. The first is a **System and Method for Generating a Jittered Test Signal**, which introduces a multi-speed jittered signal generator. This generator creates a high-quality, full-speed jittered signal by scaling a low-speed jittered signal through a frequency scaler. Unlike conventional methods, Duerden’s approach injects modulation signals into a reference signal using a jitter injector. This novel method provides superior jitter signals, making it ideal for testing advanced circuitry such as high-speed serializer/deserializer components.

The second invention is a **System and Method for Testing Integrated Circuits**. This invention features a module containing an integrated testing system equipped with one or more measurement engines closely coupled with a compute engine. The measurement engines include stimulus instruments that excite the device-under-test with various stimulus signals, as well as measurement instruments that assess the device's response and generate critical measurement data. The compute engine, with its computation logic circuitry, evaluates the device-under-test’s performance, determining whether it passes or fails. Additionally, it boasts a communications engine that provides seamless two-way communication between the integrated testing system and any associated user interfaces.

Career Highlights

Geoffrey D Duerden is currently associated with DFT Microsystems, Inc., where he continues to push the boundaries of technology in integrated circuit testing. His work has garnered respect within the electronics community, placing him at the forefront of innovation in this vital area.

Collaborations

Throughout his career, Duerden has collaborated with notable professionals, including Mohamed M Hafed and Gordon W Roberts. These partnerships have facilitated the exchange of ideas and have been instrumental in driving forward their shared goals in advancing technology.

Conclusion

Geoffrey D Duerden's contributions to electronic testing represent a fusion of innovation and practicality. His patents not only showcase his inventive talent but also provide significant advancements that support the complexity of modern circuitry. As the industry continues to evolve, Duerden’s work stands as a testament to the importance of innovation in enhancing electronic performance and reliability.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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