For the Inventor, By the Inventor

Enter inventor name

San Jose, CA, United States of America

Gary W Tietz

USPTO Granted Patents = 5

Average Co-Inventor Count = 1.5

ph-index = 4

Forward Citations = 125(Granted Patents)

Location History:

San Jose, CA (US) (1977 - 1980)
Cupertino, CA (US) (1989 - 1991)

Company Filing History:

National Semiconductor Corporation

Years Active: 1977-1991

Loading Chart...

5 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 4984255 - Edge transition insensitive delay line system and method (1991-01-08),

2. 4814726 - Digital phase comparator/charge pump with zero deadband and minimum (1989-03-21),

3. 4193007 - Emitter coupled logic master-slave flip-flop with emitter-follower clock (1980-03-11),

4. 4122405 - Digital logic level signal indication of phase and frequency lock (1978-10-24),

5. 4045689 - Circuit for squaring the transfer characteristics of a TTL gate (1977-08-30),

This text is generated by artificial intelligence and may not be accurate.

Please report any incorrect information to support@idiyas.com

Loading…