Emitter coupled logic master-slave flip-flop with emitter-follower clock

Abstract

A master-slave flip-flop, wherein a master latch circuit and a slave latch circuit each include only one pair of single-emitter bipolar transistors and one pair of dual-emitter bipolar emitter-follower transistors, is disclosed. In each circuit the first emitters of the dual-emitter transistors are cross-coupled to the bases of the single emitter transistors, and the bases of the dual-emitter transistors are coupled to the collectors of the single-emitter transistors. In the master latch circuit the bases of the single-emitter transistors are respectively coupled to complementary data input terminals. The bases of the single-emitter transistors in the slave latch circuit are coupled to the second emitters of the dual-emitter transistors of the master latch circuit. The second emitters of the dual-emitter transistors of the slave latch circuit are coupled to complementary output terminals. The emitter-follower transistors of the master and slave latch circuits are respectively clocked by complementary clock signals. During one clock signal interval the master latch circuit latches the complementary data signals from the complementary data input terminals onto the second emitter terminals of its emitter-follower transistors, while the signal state on the complementary output terminals from the slave latch circuit remains unchanged. During the complementary clock signal interval the data signals from the second emitter terminals of the master latch circuit are latched onto the complementary output terminals.