National Semiconductor Corporation

Gary W Tietz

Craig M Davis

David A Byrd

Keith James Mueller

A system (100, 50, 300) for recovering a clock signal from a serial data signal (102) having rising (204) and falling (206) transitions. The transistions (204, 206) are detected by a transition detector (11, 12, 108, 110) which generates a transition signal (13a, 13b, 109, 111) having a first logic state when a rising (204) or falling (206) transition is detected. The system (100, 50, 300) includes a delay device (22, 120, 122) which delays the transition signal (13a, 13b, 109, 111) by a preselected time period and a gating device (24, 124, 126) responsive to the transition signal (13a, 13b, 109, 111). The gating device (24, 124, 126) is enabled by the transition signal (13a, 13b, 109, 111) when the signal is the first logic state, thereby permitting a system generated clock signal (148) to propagate to a phase comparison system (132, 134, 176, 178, G 1, G4) for comparison with the delayed transition signal (23, 128, 130). The phase comparison system (132, 134, 178, G1, G4) generate a correction signal (30) indicative of the phase difference between the compared signals (23, 25, 144, 152, 130, 154) such that the transitions in clock signal (148) generated are in synchronization with the data transitions (204, 206).

Edge transition insensitive delay line system and method

A phase detector and charge pump combination is disclosed for use in a digital phase locked loop system. The phase detector includes a reset circuit that responds to the charge pump condition where it is simultaneously sourcing and sinking current. The pump up and down circuits are fast acting and balanced so that minimum conduction is employed for the phase lock condition.

Digital phase comparator/charge pump with zero deadband and minimum

A master-slave flip-flop, wherein a master latch circuit and a slave latch circuit each include only one pair of single-emitter bipolar transistors and one pair of dual-emitter bipolar emitter-follower transistors, is disclosed. In each circuit the first emitters of the dual-emitter transistors are cross-coupled to the bases of the single emitter transistors, and the bases of the dual-emitter transistors are coupled to the collectors of the single-emitter transistors. In the master latch circuit the bases of the single-emitter transistors are respectively coupled to complementary data input terminals. The bases of the single-emitter transistors in the slave latch circuit are coupled to the second emitters of the dual-emitter transistors of the master latch circuit. The second emitters of the dual-emitter transistors of the slave latch circuit are coupled to complementary output terminals. The emitter-follower transistors of the master and slave latch circuits are respectively clocked by complementary clock signals. During one clock signal interval the master latch circuit latches the complementary data signals from the complementary data input terminals onto the second emitter terminals of its emitter-follower transistors, while the signal state on the complementary output terminals from the slave latch circuit remains unchanged. During the complementary clock signal interval the data signals from the second emitter terminals of the master latch circuit are latched onto the complementary output terminals.

Emitter coupled logic master-slave flip-flop with emitter-follower clock

A digital logic level signal indicates whether a first signal in a phase-locked loop is locked in phase and frequency with a second signal provided to the loop. The digital logic level signal is provided from the sequentially last stage of a counter having a predetermined number of stages. The counter counts cycles in an input signal corresponding to one of the first signal and the second signal. A reset signal pulse having a first predetermined duration is provided to the counter from a pulse width discriminator when the pulse width discriminator detects a phase difference between the first and second signals of greater than a second predetermined duration. The reset signal pulse resets the counter. The digital logic level signal is in a state indicating an in-lock condition when a predetermined number of input signal cycles occur without the counter being reset.

Digital logic level signal indication of phase and frequency lock

A TTL gate circuit is provided with an additional transistor biased by the base of the input transistor. This additional transistor supplies current to the phase splitter emitter load, to thereby bias the phase splitter transistor off until the input voltage is high enough to turn both the phase splitter transistor and the output transistor on. The result is a substantially square voltage transfer characteristic.

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San Jose, CA, United States of America

Gary W Tietz