The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 1978
Filed:
Oct. 21, 1977
Gary William Tietz, San Jose, CA (US);
Keith James Mueller, San Jose, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A digital logic level signal indicates whether a first signal in a phase-locked loop is locked in phase and frequency with a second signal provided to the loop. The digital logic level signal is provided from the sequentially last stage of a counter having a predetermined number of stages. The counter counts cycles in an input signal corresponding to one of the first signal and the second signal. A reset signal pulse having a first predetermined duration is provided to the counter from a pulse width discriminator when the pulse width discriminator detects a phase difference between the first and second signals of greater than a second predetermined duration. The reset signal pulse resets the counter. The digital logic level signal is in a state indicating an in-lock condition when a predetermined number of input signal cycles occur without the counter being reset.