Eric Perozziello

Title: Eric Perozziello: Innovator in Semiconductor Technology

Introduction

Eric Perozziello is a notable inventor based in Half Moon Bay, California. He has made significant contributions to the field of semiconductor technology, holding two patents that showcase his innovative approach to solving complex engineering challenges.

Latest Patents

Eric's latest patents include "Patterning 3D Features in a Substrate" and "Scanning Capacitance Sample Preparation Technique." The first patent discloses methods for forming a 3D structure in a substrate, where a layer of resist is deposited and patterned to define an edge at a predetermined location. The resist is then reflowed to create a tapered region, allowing for the formation of an angled surface through concurrent etching. The second patent addresses the need for reliable measurement of electrical charge distribution in semiconductor processing. It introduces a technique for creating a precisely-located, atomically smooth cross-section of a crystalline sample, suitable for Scanning Capacitance Microscopy analysis.

Career Highlights

Eric has worked with prominent organizations such as Applied Materials, Inc. and Leland Stanford Junior University. His experience in these institutions has allowed him to refine his skills and contribute to advancements in semiconductor technology.

Collaborations

Throughout his career, Eric has collaborated with talented individuals, including Thomas Joseph Kropewnicki and Gregory L. Wojcik. These collaborations have further enriched his work and fostered innovation in the field.

Conclusion

Eric Perozziello's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor. His work continues to impact the industry, paving the way for future advancements.