Leland Stanford Junior University

Applied Matrials, Inc.

Eric Perozziello

Andreas Goebel

Claes H Bjorkman

Gregory L Wojcik

Thomas Joseph Kropewnicki

Guanyuan Michael Yu

Methods of forming a 3D structure in a substrate are disclosed. A layer of resist is deposited on the substrate. The layer of resist is patterned to define an edge at a predetermined location. The resist is reflowed to form a tapered region extending from the etch. Both the reflowed resist and the substrate are concurrently etched to transfer the tapered profile of the reflowed resist into the underlying substrate to form an angled surface. The etching is discontinued before all of the resist is consumed by the etching.

Patterning 3D features in a substrate

Currently semiconductor processing and device manufacturing relies heavily on continued scaling of critical dimensions for cost reduction and performance enhancement. In order to continue this scaling below 0.1 micron with acceptable manufacturing yields, reliable measurement of electrical charge distribution and the placement of dopants is essential, yet no conventional technique exists to obtain distortion-free cross-sectional images. An aspect of the invention relates to a technique for forming a precisely-located, substantially atomically smooth cross-section of a crystalline sample suitable for Scanning Capacitance Microscopy analysis. Another aspect of the invention provides a method for deconvolving Scanning Capacitance raw data into an accurate representation of electrical carrier distributions suitable for the higher resolution attainable with the new sample preparation technique.

Scanning capacitance sample preparation technique

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Half Moon Bay, CA, United States of America

Eric Perozziello