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For the Inventor, By the Inventor

Portland, OR, United States of America

Dinesh Somasekhar

This inventor holds 119 USPTO granted patents and 12 published patent applications and 3 EPO patents, primarily in Memory Technology (CPC class G11C7-00). Top assignees: Intel Corporation, Globalfoundries Inc., Sk Hynix Nand Product Solutions Corp.. Active years: 1999-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dinesh Somasekhar. Retrieved from https://idiyas.com/inventor/dinesh-somasekhar

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 119 

% Patents Active = 52.1

 

Average Co-Inventor Count = 4.4

ph-index = 23

Forward Citations = 1,788(Granted Patents)

Forward Citations (Not Self Cited) = 1,654(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Lafayette, IN (US) (1999)
  • Hillsboro, OR (US) (2002 - 2007)
  • Portland, OR (US) (2005 - 2023)

Company Filing History:

goldMedal113 out of 56,290 
 
Intel Corporation
 patents
silverMedal5 out of 5,671 
 
Globalfoundries Inc.
 patents
bronzeMedal1 out of 137 
 
Sk Hynix Nand Product Solutions Corp.
 patents

Years Active: 1999-2025

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Areas of Expertise:
Memory Repair
Error Correction Code
Integrated Circuits
Multi-Bit Devices
Data Multiplexer
Low Latency
FinFET Architecture
Voltage Control
Charge Recovery
NAND Logic
DRAM Cell
Interconnect Designs
119 patents (USPTO):Explore Patents
1. 12451212 - Device, system and method for memory repair with multi-cell switching (2025-10-21),
2. 12166480 - Data multiplexer single phase flip-flop (2024-12-10),
3. RE49439 - Scalable polylithic on-package integratable apparatus and method (2023-02-27),
4. 11476185 - Innovative way to design silicon to overcome reticle limit (2022-10-18),
5. 11152060 - Multi-bit read-only memory device (2021-10-19),
6. 10884853 - Fast search of error correction code (ECC) protected data in a memory (2021-01-05),
7. 10862622 - Error correction code (ECC) and data bus inversion (DBI) encoding (2020-12-08),
8. 10860419 - Minimal aliasing bit-error correction code (2020-12-08),
9. 10853300 - Low latency statistical data bus inversion for energy reduction (2020-12-01),
10. 10347309 - Digitally trimmable integrated resistors including resistive memory elements (2019-07-09),
11. 10319461 - Low-overhead mechanism to detect address faults in ECC-protected memories (2019-06-11),
12. 9998401 - Architecture for on-die interconnect (2018-06-12),
13. 9992135 - Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces (2018-06-05),
14. 9948179 - Apparatus for charge recovery during low power mode (2018-04-17),
15. 9870012 - Digitally phase locked low dropout regulator apparatus and system using ring oscillators (2018-01-16),

Title: Dinesh Somasekhar - Innovative Inventor from Portland

Introduction: Dinesh Somasekhar is a talented inventor based in Portland, Oregon, known for his groundbreaking contributions to various fields.

Latest Patents: Dinesh Somasekhar holds several patents in the areas of renewable energy technologies, sustainable agriculture, and advanced medical devices.

Career Highlights: With a background in engineering and a passion for problem-solving, Dinesh has successfully developed and patented innovative solutions that have the potential to revolutionize industries.

Collaborations: Throughout his career, Dinesh has collaborated with leading research institutions, universities, and companies to bring his inventions to life and make a positive impact on society.

Conclusion: Dinesh Somasekhar's dedication to innovation and his commitment to creating a better future through his inventions make him a truly inspiring figure in the world of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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