Intel Corporation

Globalfoundries Inc.

Sk Hynix Nand Product Solutions Corp.

Dinesh Somasekhar

Vivek K De

Yibin Ye

Muhammad M Khellah

Stephen H Tang

Ali Keshavarzi

Fabrice Paillet

Shih-Lien L Lu

James W Tschanz

Brian S Doyle

Fatih Hamzaoglu

Nam Sung Kim

Suman Datta

Jaydeep P Kulkarni

Robert S Chau

Gerhard Schrom

Kevin X Zhang

Sriram R Vangal

Mohsen Alavi

Vivek Joy Kozhikkottu

Surhud Khare

Tanay Karnik

Jongwook Kye

Ashoke Ravi

Shekhar Yeshwant Borkar

Wei Wu

David Stewart Dunning

Nick Lindert

Balaji Srinivasan

Youngtag Woo

Ankit More

Gunjan H Pandya

Shankar Ganesh Ramasubramanian

Swaroop Ghosh

Gilbert W Dewey

Swaminathan Sivakumar

Peter Hazucha

Alaa R Alameldeen

Zeshan A Chishti

Ganesh Balamurugan

Yunfei Deng

Tawfiq Musah

Tzu-Chien Hsueh

Bo Zheng

Amaresh Pangal

Pascal A Meinerzhagen

Melin Dadual

Sudip Shekhar

Kon-Woo Kwon

Jack T Kavalieros

Ravi Pillarisetty

Niloy Mukherjee

Ram K Krishnamurthy

Uday Shah

Uygar E Avci

Christopher B Wilkerson

Yan E Wang

Christopher J Jezewski

Sourav Saha

Mahbub Rashed

Suresh Venkatesan

Dheeraj R Subbareddy

Steven Hsu

Yih Wang

Konrad K Lai

Andy C Wei

Md Altaf Hossain

Subramani Kengeri

Peter L D Chang

Krishnamurthy Soumyanath

Navneet Jain

Jianping Xu

Juhan Kim

Atila Alvandpour

Nitin Y Borkar

Carlos Alfonso Tokunaga

Arijit Raychowdhury

Eric A Karl

Richard B Nicholls

Yatin Hoskote

Zheng Guo

Cyrille Dray

Chris Wilkerson

David Doman

M Clair Webb

Clifford L Ong

Sung Tae Moon

Mostafa Elmala

Yorgos Palaskas

Amit R Trivedi

Ali R Farhang

Kaitlyn Chen

Gopal Srinivasan

Stephen Wu

Gregory E Ruhl

Venkat S Veeramachaneni

Subi Kengeri

Jaydeep P Kulkami

Meterelliyoz Mesut

Jon Stephan

Techniques and mechanisms for a memory device to support memory repair functionality for a column of a memory array. In an embodiment, the column comprises first memory cells and second memory cells, where switch circuitry is coupled between multiple signal lines and the column. Control circuitry transitions the switch circuitry to a state which corresponds to a defective one of the first cells. The state switchedly decouples the defective cell, and an adjoining one of the first cells, each from respective ones of the signal lines. During the state, two or more of the signal lines are able to communicate each to a different respective one of the second cells. In another embodiment, the switch circuitry is transitioned to the state based on an identifier of the defective cell, and independent of whether any other cell of the column has been identified as defective.

Device, system and method for memory repair with multi-cell switching

A single-phase clocked data multiplexer (MUX-D) scan capable flipflop (FF) design that improves over existing transmission-gate (t-gate) based master-slave flipflops in terms of dynamic capacitance (Cdyn) as well as performance while remaining comparable in area. Unique features of the design are a complementary metal oxide semiconductor (non-t-gate) style structure with an improvement in circuit parameters achieved by eliminating clock inversions and maximally sharing NMOS devices across NAND structures. The core of the flipflop adopts an all CMOS NAND, And-OR-Inverter (AOI) complex logic structure to implement a true edge-triggered flip-flop functionality.

Data multiplexer single phase flip-flop

Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

Scalable polylithic on-package integratable apparatus and method

Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.

Innovative way to design silicon to overcome reticle limit

Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.

Multi-bit read-only memory device

An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.

Fast search of error correction code (ECC) protected data in a memory

Embodiments may relate to a processor to an electronic device that includes an error correction code (ECC) encoder that is to perform ECC encoding on aa data message to generate an ECC encoded data message. The electronic device may further include a data bus inversion (DBI) encoder communicatively coupled with the ECC encoder, wherein the DBI encoder is to perform DBI encoding on the ECC encoded data message to generate a DBI encoded data message. Other embodiments may be described or claimed.

Error correction code (ECC) and data bus inversion (DBI) encoding

Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.

Minimal aliasing bit-error correction code

In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.

Low latency statistical data bus inversion for energy reduction

Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions (MTJs). The resistance of the resistive memory elements may be digitally trimmable to adjust a resistance of the resistor on the signal path. The resistor may be incorporated into an analog or mixed signal circuit to pass an analog signal on the signal path. Other embodiments may be described and claimed.

Digitally trimmable integrated resistors including resistive memory elements

Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.

Low-overhead mechanism to detect address faults in ECC-protected memories

In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

Architecture for on-die interconnect

Described is an apparatus which comprises: a Network-On-Chip fabric using crossbar switches, having distributed ingress and egress ports; and a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include: a dual-mode circuitry; a controller operable to: configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively.

Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces

Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.

Apparatus for charge recovery during low power mode

Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.

Digitally phase locked low dropout regulator apparatus and system using ring oscillators

Growing community of inventors

Portland, OR, United States of America

Dinesh Somasekhar