David J Gurney

Title: David J. Gurney: Inventor in Integrated-Circuit Design

Introduction

David J. Gurney is an inventor based in West Linn, Oregon, whose work includes methods for analyzing circuit layouts and improving parasitic capacitance extraction in integrated circuits. His listed portfolio includes 3 patents.

Latest Patents

Selective Parasitic Extraction. This invention describes a computing system that preprocesses a circuit’s physical layout to identify attributes of its nets, including their locations and total capacitances. It orders net extraction using a space-filling curve, taking net locations and coupling capacitances into account. The system can selectively decouple nets based on their total capacitances, generate electrical representations of extracted nets, and write those representations to a circuit netlist.

Capacitance Extraction of Integrated Circuits with Floating Fill. This invention aims to improve the accuracy of parasitic capacitance extraction for integrated-circuit designs containing floating fill. It uses a fill-net elimination method: capacitances to a variable level are extracted, while remaining capacitances are approximated.

Career Highlights

Gurney’s listed professional experience includes Mentor Graphics Corporation. His work on circuit-layout analysis and capacitance extraction addresses technical challenges in integrated-circuit design.

Collaborations

His listed coworkers include Sandeep Koranne and Mingchao Wang.

Conclusion

David J. Gurney’s patent work focuses on selective parasitic extraction and more accurate capacitance modeling for integrated circuits, reflecting contributions to the analysis of complex circuit designs.