Mentor Graphics Corporation

Other

David J Gurney

Sandeep Koranne

Mingchao Wang

This application discloses a computing system to pre-process a physical or geometric layout of a circuit design to determine various attributes of the nets, such as a location and a total capacitance for each net in the geometric layout. The computing system can order extraction of the nets from the geometric layout of the circuit design with a space filling curve based, at least in part, on the locations of the nets in the geometric layout of the circuit design and any coupling capacitance between the nets in the geometric layout of the circuit design. The computing system can selectively decouple nets with a coupling capacitance based, at least in part, on the total capacitance for the nets associated with the coupling capacitance. The computing system can generate an electrical representation for each of the extracted nets and write them to a netlist for the circuit design.

Selective parasitic extraction

The present invention improves the accuracy of parasitic capacitance extraction of IC designs with floating fill. One embodiment of the present invention approximates the coupling capacitances of fill nets beyond an exact-approximation level by a fill net elimination method whereby actual capacitances of the fill net to the variable level are fully extracted and remaining capacitances are approximated.

Capacitance extraction of intergrated circuits with floating fill

An IC design computer simulation tool is provided with a design reader equipped to assign device characterizations to electronic devices of an IC design, and model evaluators equipped to adaptively perform model evaluations in accordance with the electronic devices' assigned device characterizations. In one embodiment, the electronic devices include transistors, and the adaptive model evaluations provide evaluated model quantities to support solution of the circuit node voltages using fully coupled (implicit) or partially decoupled (explicit) solution techniques. In particular, the transistor capacitive coupling currents are expressed according to the assigned device characterizations.

Growing community of inventors

West Linn, OR, United States of America

David J Gurney