The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Dec. 27, 2013
Applicant:

Mentor Graphics Corporation, Wllsonville, OR (US);

Inventors:

David J. Gurney, Portland, OR (US);

Sandeep Koranne, West Linn, OR (US);

Mingchao Wang, Tigard, OR (US);

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5036 (2013.01);
Abstract

This application discloses a computing system to pre-process a physical or geometric layout of a circuit design to determine various attributes of the nets, such as a location and a total capacitance for each net in the geometric layout. The computing system can order extraction of the nets from the geometric layout of the circuit design with a space filling curve based, at least in part, on the locations of the nets in the geometric layout of the circuit design and any coupling capacitance between the nets in the geometric layout of the circuit design. The computing system can selectively decouple nets with a coupling capacitance based, at least in part, on the total capacitance for the nets associated with the coupling capacitance. The computing system can generate an electrical representation for each of the extracted nets and write them to a netlist for the circuit design.


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