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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

David G Reed

This inventor holds 46 USPTO granted patents and 1 published patent application and 2 EPO patents, primarily in Memory Management. Top assignee: Nvidia Corporation. Active years: 2001-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: David G Reed. Retrieved from https://idiyas.com/inventor/david-g-reed

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 46 

% Patents Active = 91.3

 

Average Co-Inventor Count = 2.3

ph-index = 11

Forward Citations = 372(Granted Patents)


Location History:

  • Saratoga, CA (US) (2003 - 2020)
  • Santa Clara, CA (US) (2001 - 2022)

Company Filing History:

goldMedal46 out of 6,228 
 
Nvidia Corporation
 patents

Years Active: 2001-2022

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Areas of Expertise:
Memory Management Systems
DRAM Error Correction
Data Compression
Graphics Processing
Power Management
Bus Fabric
Chipset Security
Virtual Channel Communication
Screen Compression
High-Speed Interface
Memory Address Multiplexing
Graphics Device Clustering
46 patents (USPTO):Explore Patents
1. 11256568 - Memory management systems and methods (2022-02-22),
2. 10783950 - Memory management systems and methods using a management communication bus (2020-09-22),
3. 10528423 - Memory management systems and methods (2020-01-07),
4. 10445177 - Controller-based memory scrub for DRAMs with internal error-correcting code (ECC) bits contemporaneously during auto refresh or by using masked write commands (2019-10-15),
5. 10049006 - Controller-based memory scrub for DRAMs with internal error-correcting code (ECC) bits contemporaneously during auto refresh or by using masked write commands (2018-08-14),
6. 10002586 - Compression of display data stored locally on a GPU (2018-06-19),
7. 9880900 - Method for scrubbing and correcting DRAM memory data with internal error-correcting code (ECC) bits contemporaneously during self-refresh state (2018-01-30),
8. 9823964 - Method for memory scrub of DRAM with internal error correcting code (ECC) bits during either memory activate and/or precharge operation (2017-11-21),
9. 9262837 - PCIE clock rate stepping for graphics and platform processors (2016-02-16),
10. 8738945 - Using non-lossless compression to save power (2014-05-27),
11. 8736617 - Hybrid graphic display (2014-05-27),
12. 8692837 - Screen compression for mobile applications (2014-04-08),
13. 8635480 - Method and apparatus for controlling power to a processing unit (2014-01-21),
14. 8532098 - System and method for virtual channel communication (2013-09-10),
15. 8473750 - Chipset security offload engine (2013-06-25),

Title: The Innovative Journey of David G Reed

Introduction: David G Reed, a pioneering inventor based in Santa Clara, CA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: David G Reed's latest patents include cutting-edge advancements in artificial intelligence, renewable energy technologies, and smart home systems, solidifying his reputation as a forward-thinker in the industry.

Career Highlights: With a career spanning over two decades, David G Reed has held key positions in leading tech companies, where he spearheaded research and development projects that have resulted in numerous successful patents and products that have revolutionized the market.

Collaborations: Throughout his career, David G Reed has collaborated with top engineers, scientists, and designers, fostering a culture of innovation and creativity that has led to the development of groundbreaking technologies that have shaped the industry.

Conclusion: David G Reed's relentless pursuit of innovation and his passion for pushing the boundaries of technology have established him as a visionary inventor whose work continues to inspire and drive progress in the ever-evolving tech landscape.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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