The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Dec. 08, 2015
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

David Reed, Saratoga, CA (US);

Alok Gupta, Fremont, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 29/04 (2006.01); G11C 7/02 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0688 (2013.01); G11C 7/02 (2013.01); G11C 11/4082 (2013.01); G11C 11/4087 (2013.01); G11C 11/4093 (2013.01); G11C 11/40615 (2013.01); G11C 29/04 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01); G11C 2029/4402 (2013.01); G11C 2211/4062 (2013.01);
Abstract

A method for updating a DRAM memory array is disclosed. The method comprises: a) receiving a command from a memory controller to initiate an active cycle for activating a memory row in a DRAM memory array; b) performing an Error Correction Code (ECC) scrub on the memory row prior to reading data from the memory row into sense amplifiers in the DRAM memory array in accordance with the command to activate; c) activating the memory row; and d) writing corrected data following the ECC scrub back into memory from the sense amplifiers during a pre-charge cycle of the DRAM memory array.


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