The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2018
Filed:
Dec. 08, 2015
Applicant:
Nvidia Corporation, Santa Clara, CA (US);
Inventors:
David Reed, Saratoga, CA (US);
Alok Gupta, Fremont, CA (US);
Assignee:
NVIDIA CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G06F 11/10 (2006.01); G11C 29/04 (2006.01); G11C 7/02 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G11C 7/02 (2013.01); G11C 11/4082 (2013.01); G11C 11/4087 (2013.01); G11C 11/4093 (2013.01); G11C 11/40615 (2013.01); G11C 29/04 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01); G11C 2029/4402 (2013.01); G11C 2211/4062 (2013.01);
Abstract
In one embodiment, a method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a self-refresh state after a period of inactivity; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry; and c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in an activated row of the DRAM memory array.