The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2019
Filed:
Jul. 03, 2018
Applicant:
Nvidia Corporation, Santa Clara, CA (US);
Inventors:
David Reed, Santa Clara, CA (US);
Alok Gupta, Santa Clara, CA (US);
Assignee:
Nvidia Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 29/04 (2006.01); G11C 7/02 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G06F 11/106 (2013.01); G11C 7/02 (2013.01); G11C 11/4082 (2013.01); G11C 11/4087 (2013.01); G11C 11/4093 (2013.01); G11C 11/40615 (2013.01); G11C 29/04 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01); G11C 2029/4402 (2013.01); G11C 2211/4062 (2013.01);
Abstract
A method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data into an associated sense amplifier buffer; and c) during the refresh, performing an ERR Correction Code (ECC) scrub operation of selected bits in the activated row of the DRAM memory array.