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For the Inventor, By the Inventor

Boise, ID, United States of America

Dale Herber Hiscock

This inventor holds 22 USPTO granted patents and 4 published patent applications, primarily in Memory Technology. Top assignees: Micron Technology Incorporated, Lodestar Licensing Group LLC. Active years: 2018-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dale Herber Hiscock. Retrieved from https://idiyas.com/inventor/dale-herber-hiscock

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 22 

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 3

Forward Citations = 26(Granted Patents)


Company Filing History:

goldMedal19 out of 39,222 
 
Micron Technology Incorporated
 patents
silverMedal2 out of 218 
 
Lodestar Licensing Group LLC
 patents
where one patent can have more than one assignee

Years Active: 2018-2026

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Areas of Expertise:
Memory Refresh
TSV Delay
Die Selection
Partial Array
Powerup Delay
Health Monitor
Data Transfer
Adaptive Routing
Activation Improvements
Bank Refresh
Programmable Stagger
Logic Defects
22 patents (USPTO):Explore Patents
1. 12524342 - Memory with post-packaging master die selection (2026-01-13),
2. 12431180 - Memory with programmable die refresh stagger (2025-09-30),
3. 12300301 - Memory with partial array refresh (2025-05-13),
4. 11908508 - Memory with partial array refresh (2024-02-20),
5. 11868252 - Memory with post-packaging master die selection (2024-01-09),
6. 11670358 - Memory with adjustable TSV delay (2023-06-06),
7. 11581031 - Memory with partial bank refresh (2023-02-14),
8. 11482271 - Memory with programmable die refresh stagger (2022-10-25),
9. 11393790 - Memory with TSV health monitor circuitry (2022-07-19),
10. 11282562 - Refresh-related activation improvements (2022-03-22),
11. 11276454 - Memory with partial array refresh (2022-03-15),
12. 11250890 - Memory with configurable die powerup delay (2022-02-15),
13. 11145352 - Memory with adjustable TSV delay (2021-10-12),
14. 11062755 - Memory with partial bank refresh (2021-07-13),
15. 11024367 - Memory with on-die data transfer (2021-06-01),

Title: Spotlight on Innovator Dale Herber Hiscock

Introduction:

Dale Herber Hiscock is a brilliant inventor based in Boise, ID (US), with a notable portfolio of 18 patents to his name. His cutting-edge work in the field of memory technology has garnered widespread recognition and acclaim.

Latest Patents:

Among his latest patents is the groundbreaking "Memory with post-packaging master die selection," which revolutionizes memory devices and systems. This patent introduces a unique method for post-packaging master die selection, enhancing the efficiency and functionality of memory devices.

Additionally, Hiscock is the mastermind behind the "Memory with adjustable TSV delay" patent. This innovation focuses on memory devices with adjustable through-silicon via (TSV) delay, offering a novel approach to aligning internal timings of memory dies within a device.

Career Highlights:

Dale Herber Hiscock is a key figure at Micron Technology Incorporated, a leading technology company at the forefront of advancements in memory and storage solutions. His contribution to the company's research and development efforts has been instrumental in driving innovation and pushing the boundaries of what is possible in the industry.

Collaborations:

Throughout his career, Hiscock has collaborated closely with esteemed colleagues such as Joshua E Alzheimer and Michael Kaminski. Together, they have worked on cutting-edge projects and brought to life revolutionary ideas that have shaped the landscape of memory technology.

Conclusion:

In conclusion, Dale Herber Hiscock stands out as a visionary inventor with a remarkable track record of patents that have redefined the field of memory technology. His relentless pursuit of innovation and commitment to pushing boundaries continue to inspire and influence the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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