The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Dec. 06, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Dale H. Hiscock, Boise, ID (US);

Evan C. Pearson, Boise, ID (US);

John H. Gentry, Boise, ID (US);

Michael J. Scott, Boise, ID (US);

Greg S. Gatlin, Mountain Home, ID (US);

Lael H. Matthews, Meridian, ID (US);

Anthony M. Geidl, Boise, ID (US);

Michael Roth, Boise, ID (US);

Markus H. Geiger, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/66 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 22/14 (2013.01); H01L 22/34 (2013.01); H01L 25/50 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06596 (2013.01);
Abstract

Memory devices and systems with TSV health monitor circuitry, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies, a plurality of through-silicon vias (TSVs) in electrical communication with the memory dies; and circuitry. In some embodiments, the circuitry is configured to electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit. For example, the circuitry can activate a transistor electrically positioned between TSVs of the pair of TSVs to electrically couple the pair of TSVs. In these and other embodiments, the circuitry applies a test voltage to the pair of TSVs using the passive circuit to determine whether a TSV of the pair of TSVs includes degradation.


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