The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Dec. 06, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

John H. Gentry, Boise, ID (US);

Michael J. Scott, Boise, ID (US);

Greg S. Gatlin, Mountain Home, ID (US);

Lael H. Matthews, Meridian, ID (US);

Anthony M. Geidl, Boise, ID (US);

Michael Roth, Boise, ID (US);

Markus H. Geiger, Boise, ID (US);

Dale H. Hiscock, Boise, ID (US);

Evan C. Pearson, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/4076 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06541 (2013.01);
Abstract

Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.


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