logo

For the Inventor, By the Inventor

Gyeonggi-do, South Korea

Dae Woong Lee

This inventor holds 10 USPTO granted patents and 17 published patent applications. Top assignees: Skhynix Inc., Hynix Semiconductor Inc.. Active years: 2007-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dae Woong Lee. Retrieved from https://idiyas.com/inventor/dae-woong-lee-qowyj05e

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 10 

% Patents Active = 80.0

Average Co-Inventor Count = 1.9

ph-index = 3

Forward Citations = 21(Granted Patents)


Location History:

  • Kyoungki-do, KR (2007 - 2008)
  • Gyeonggi-do, KR (2012 - 2014)
  • Yongin-si, KR (2014 - 2017)
  • Hwaseong-si, KR (2019 - 2020)

Company Filing History:

goldMedal6 out of 11,696 
 
Skhynix Inc.
 patents
silverMedal4 out of 6,228 
 
Hynix Semiconductor Inc.
 patents

Years Active: 2007-2020

Loading Chart...
10 patents (USPTO):Explore Patents
1. 10714405 - Semiconductor packages relating to thermal redistribution patterns (2020-07-14),
2. 10410947 - Semiconductor packages relating to thermal redistribution patterns (2019-09-10),
3. 9659833 - Semiconductor packages, methods of manufacturing the same, electronic systems including the same, and memory cards including the same (2017-05-23),
4. 9543251 - Semiconductor chip and semiconductor package having the same (2017-01-10),
5. 8810309 - Stack package and method for selecting chip in stack package (2014-08-19),
6. 8680688 - Stack package having flexible conductors (2014-03-25),
7. 8288873 - Stack package having flexible conductors (2012-10-16),
8. 8164200 - Stack semiconductor package and method for manufacturing the same (2012-04-24),
9. 7462508 - Stack type semiconductor package module utilizing solder coated stacking protrusions and method for manufacturing the same (2008-12-09),
10. 7301234 - Stack type semiconductor package module utilizing solder coated stacking protrusions and method for manufacturing the same (2007-11-27),

Title: Dae Woong Lee: Innovator in Semiconductor Technology

Introduction

Dae Woong Lee is a prominent inventor based in Gyeonggi-do, South Korea. He has made significant contributions to the field of semiconductor technology, holding a total of 10 patents. His work focuses on improving semiconductor packages, particularly in relation to thermal management.

Latest Patents

One of Dae Woong Lee's latest patents involves semiconductor packages that feature thermal redistribution patterns. This innovative design includes a first semiconductor chip and a second semiconductor chip, both of which are placed on a package substrate. The thermal redistribution pattern is designed with a first end portion located in a high-temperature region adjacent to the first semiconductor chip, a second end portion in a low-temperature region near the second semiconductor chip, and an extension portion that connects the two end portions. This design aims to enhance the efficiency and reliability of semiconductor packages.

Career Highlights

Throughout his career, Dae Woong Lee has worked with leading companies in the semiconductor industry, including SK Hynix Inc. and Hynix Semiconductor Inc. His experience in these organizations has allowed him to develop and refine his innovative ideas in semiconductor technology.

Collaborations

Dae Woong Lee has collaborated with notable colleagues such as Tae Min Kang and Byoung Do Lee. These partnerships have contributed to the advancement of semiconductor technologies and have fostered a collaborative environment for innovation.

Conclusion

Dae Woong Lee's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the field. His work continues to influence the development of efficient semiconductor packages, showcasing the importance of innovation in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…