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Puyallup, WA, United States of America

Craig M Davis

This inventor holds 9 USPTO granted patents. Top assignee: National Semiconductor Corporation. Active years: 1989-2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Craig M Davis. Retrieved from https://idiyas.com/inventor/craig-m-davis

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 9

% Patents Active = 100.0

Average Co-Inventor Count = 1.9

ph-index = 8

Forward Citations = 251(Granted Patents)

Location History:

Santa Clara, CA (US) (1989 - 1991)
Puyallup, WA (US) (1992 - 1999)
Englewood, CO (US) (2003)

Company Filing History:

National Semiconductor Corporation

Years Active: 1989-2003

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9 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6624707 - Method and circuit for improving lock-time performance for a phase-locked loop (2003-09-23),

2. 5907253 - Fractional-N phase-lock loop with delay line loop having (1999-05-25),

3. 5420545 - Phase lock loop with selectable frequency switching time (1995-05-30),

4. 5394114 - One nanosecond resolution programmable waveform generator (1995-02-28),

5. 5166641 - Phase-locked loop with automatic phase offset calibration (1992-11-24),

6. 5089723 - CMOS-based pseudo ECL output buffer (1992-02-18),

7. 4984255 - Edge transition insensitive delay line system and method (1991-01-08),

8. 4876519 - High frequency ECL voltage controlled ring oscillator (1989-10-24),

9. 4814726 - Digital phase comparator/charge pump with zero deadband and minimum (1989-03-21),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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