Phase lock loop with selectable frequency switching time

Abstract

A phase lock loop (PLL) circuit for controlling an oscillator includes a phase comparator, a loop filter, a reference converter and a feedback converter whose performance characteristics are dynamically controlled so as to provide a phase-locked output signal with both high frequency stepping resolution and low phase locking time. The phase comparator compares the relative phases of the reference and feedback signals, and outputs a phase difference signal representing such phase comparison. The loop filter, in accordance with a filter bandwidth dynamically selected by a filter control signal, filters the phase difference signal to provide a frequency control signal for a voltage controlled oscillator (VCO). The reference converter is a programmable frequency divider which, in accordance with a reference proportionality factor dynamically selected by a reference control signal, reduces the frequency of the PLL reference signal frequency used by the phase comparator. The feedback converter is another programmable frequency divider which, in accordance with a feedback proportionality factor dynamically determined by a feedback control signal, reduces the frequency of the VCO feedback signal frequency used by the phase comparator. Each combination of a selected filter bandwidth, a reference proportionality factor and a feedback proportionality factor corresponds to a different time interval within which phase lock is achieved.