The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 1989
Filed:
Jan. 23, 1989
Craig M Davis, Santa Clara, CA (US);
Richard R Rasmussen, Fremont, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
An emitter-coupled logic (ECL) gate configuration is provided that allows variations in the bias current for controlling propagation delay. The emitter coupled logic circuitry includes a plurality of input transistors having commonly-coupled emitters. The collector of each input transistor is connected to receive a control voltage. A current source is connected between the commonly-coupled emitters and ground. Circuitry, preferably a variable resistance, is connected between the collectors of the input transistors and a supply voltage. A bias voltage controls the charging current provided to the collectors of the ECL input transistors.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile