The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 1999
Filed:
Nov. 24, 1997
Applicant:
Inventors:
Craig Davis, Puyallup, WA (US);
Jeff Huard, Puyallup, WA (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L / ;
U.S. Cl.
CPC ...
327156 ; 327158 ; 327160 ; 331D / ; 331 44 ;
Abstract
A fractional-N phase-lock loop (PLL) with a delay line loop (DLL) having a self-calibrating fractional delay element which controls the PLL feedback signal in such a manner that the delay intervals for the feedback signal are: increased when small fractional divisors (<1/2) causing a lagging phase relationship or large fractional divisors (>1/2) causing a leading phase relationship are sensed; and decreased when small fractional divisors (<1/2) causing a leading phase relationship or large fractional divisors (>1/2) causing a lagging phase relationship are sensed.