logo

For the Inventor, By the Inventor

Shanghai, China

Chunming Wang

This inventor holds 27 USPTO granted patents and 5 published patent applications and 18 EPO patents, primarily in Non-Volatile Memory. Top assignee: Silicon Storage Technology, Inc.. Active years: 2015-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chunming Wang. Retrieved from https://idiyas.com/inventor/chunming-wang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 27 

% Patents Active = 96.3

 

Average Co-Inventor Count = 4.3

ph-index = 3

Forward Citations = 30(Granted Patents)


Company Filing History:

goldMedal27 out of 655 
 
Silicon Storage Technology, Inc.
 patents

Years Active: 2015-2026

Loading Chart...
Loading Chart...
Areas of Expertise:
Non-Volatile Memory
Split-Gate Cells
Flash Memory
High Voltage Devices
Logic Devices
Floating Gates
Polysilicon Deposition
Memory Cell Architectures
Coupling Ratio
FINFET Structures
Source Line Circuits
Twin-Bit Memory
27 patents (USPTO):Explore Patents
1. 12621990 - Split gate non-volatile memory cells, HV and logic devices with FINFET structures, and method of making same (2026-05-05),
2. 11799005 - Split-gate flash memory cell with improved control gate capacitive coupling, and method of making same (2023-10-24),
3. 11737266 - Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate (2023-08-22),
4. 11652162 - Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps (2023-05-16),
5. 11621335 - Method of making split-gate non-volatile memory cells with erase gates disposed over word line gates (2023-04-04),
6. 11538532 - Architectures for storing and retrieving system data in a non-volatile memory system (2022-12-27),
7. 11508442 - Non-volatile memory system using strap cells in source line pull down circuits (2022-11-22),
8. 11444091 - Method of making memory cells, high voltage devices and logic devices on a substrate (2022-09-13),
9. 11404545 - Method of forming split-gate flash memory cell with spacer defined floating gate and discretely formed polysilicon gates (2022-08-02),
10. 11322507 - Method of making memory cells, high voltage devices and logic devices on a substrate with silicide on conductive blocks (2022-05-03),
11. 11316024 - Split-gate non-volatile memory cells with erase gates disposed over word line gates, and method of making same (2022-04-26),
12. 11315940 - Method of forming a device with planar split gate non-volatile memory cells, high voltage devices and FinFET logic devices (2022-04-26),
13. 11315635 - Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same (2022-04-26),
14. 11081553 - Method of forming split gate memory cells (2021-08-03),
15. 10879252 - Non-volatile memory cells with floating gates in dedicated trenches (2020-12-29),

Hello! How can I assist you today?

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…