The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2026

Filed:

Jan. 30, 2023
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Guo Xiang Song, Shanghai, CN;

Chunming Wang, Shanghai, CN;

Leo Xing, Shanghai, CN;

Xian Liu, Sunnyvale, CA (US);

Nhan Do, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/42 (2023.01); H10B 41/30 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/68 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10B 41/42 (2023.02); H10B 41/30 (2023.02); H10D 30/024 (2025.01); H10D 30/0411 (2025.01); H10D 30/6211 (2025.01); H10D 30/683 (2025.01); H10D 30/6892 (2025.01); H10D 64/017 (2025.01); H10D 64/035 (2025.01);
Abstract

A method of forming memory cells, high voltage devices and logic devices on fins of a semiconductor substrate's upper surface, and the resulting memory device formed thereby. The memory cells are formed on a pair of the fins, where the floating gate is disposed between the pair of fins, the word line gate wraps around the pair of fins, the control gate is disposed over the floating gate, and the erase gate is disposed over the pair of fins and partially over the floating gate. The high voltage devices include HV gates that wrap around respective fins, and the logic devices include logic gates that are metal and wrap around respective fins.


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