Company Filing History:

5 out of 2,485

Synopsys, Inc.

patents

3 out of 2,542

Cadence Design Systems, Inc.

patents

1 out of 219

Tela Innovations, Inc.

patents

Years Active: 2005-2024

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9 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12175181 - Timing-aware surgical optimization for engineering change order in chip design (2024-12-24),

2. 8701074 - Automatic reduction of modes of electronic circuits for timing analysis (2014-04-15),

3. 8627262 - Automatic generation of merged mode constraints for electronic circuits (2014-01-07),

4. 8607186 - Automatic verification of merged mode constraints for electronic circuits (2013-12-10),

5. 8261221 - Comparing timing constraints of circuits (2012-09-04),

6. 7823098 - Method of designing a digital circuit by correlating different static timing analyzers (2010-10-26),

7. 7418684 - Systems, methods, and apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks (2008-08-26),

8. 7356451 - Assertion handling for timing model extraction (2008-04-08),

9. 6928630 - Timing model extraction by timing graph reduction (2005-08-09),

Title: Cho Moon: Innovator in Circuit Design Optimization

Introduction

Cho Moon is a prominent inventor based in San Diego, CA, known for his contributions to circuit design optimization. With a total of 9 patents, he has made significant advancements in the field of electronic circuits, particularly in timing analysis and optimization techniques.

Latest Patents

One of Cho Moon's latest patents is titled "Timing-aware surgical optimization for engineering change order in chip design." This innovative method involves optimizing a circuit layout design by identifying target and non-critical nets based on their performance characteristics. The process includes adjusting the shape and location of these nets to ensure that performance remains within specified constraints.

Another notable patent is "Automatic reduction of modes of electronic circuits for timing analysis." This patent addresses the merging of circuit modes to reduce complexity. By identifying subsets of mergeable modes and transforming constraints, the method enhances the efficiency of timing analysis in electronic circuits.

Career Highlights

Throughout his career, Cho Moon has worked with leading companies in the industry, including Synopsys, Inc. and Cadence Design Systems, Inc. His experience in these organizations has allowed him to develop and refine his innovative approaches to circuit design.

Collaborations

Cho Moon has collaborated with talented professionals such as Harish Kriplani and Sonia Singhal. These partnerships have contributed to the advancement of his research and the successful development of his patents.

Conclusion

Cho Moon's work in circuit design optimization showcases his expertise and innovative spirit. His contributions continue to influence the field, making him a notable figure in the world of electronic engineering.

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