The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Dec. 03, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Bon Woong Ku, Santa Clara, CA (US);

Nahmsuk Oh, Palo Alto, CA (US);

Cho Moon, San Jose, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/394 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/394 (2020.01);
Abstract

A method of performing an optimization within a circuit layout design is provided. The method includes determining, from multiple nets of the circuit layout design, a target net that has one or more performance characteristics that are outside a range of constraints, determining, from the multiple nets, a non-critical net that has the one or more performance characteristics that are within the range of the constraints, and adjusting, by a processor, one or more of a shape and a location of one or more of the non-critical net and the target net, such that the one or more performance characteristics of the non-critical net is changed and remains within the range of the constraints.


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