Taipei, Taiwan

Chia-Cheng Wang

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2000.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chia-Cheng Wang. Retrieved from https://idiyas.com/inventor/chia-cheng-wang-t8n8bexw

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2000

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1 patent (USPTO):Explore Patents

Title: Chia-Cheng Wang and Semiconductor Manufacturing Innovation.

Introduction

Chia-Cheng Wang is an inventor associated with Taiwan Semiconductor Manufacturing Company Ltd. in Taipei, Taiwan. His patent work addresses a semiconductor manufacturing process designed to improve the uniformity and quality of insulating layers.

Latest Patents

Wang is associated with 1 patent, titled “Process for Forming a SAUSG Inter Metal Dielectric Layer by Pre-Coating.” The invention describes forming a silicon oxide coating on the interior walls of a chemical vapor deposition reactor before processing a wafer. A first insulating layer, preferably a sub-atmospheric undoped silicon glass layer formed using TEOS, is then deposited over the semiconductor structure. The coating is intended to improve the insulating layer’s etch-rate uniformity and produce improved via and contact opening profiles.

Career Highlights

Wang’s documented patent contribution focuses on a practical challenge in semiconductor fabrication: achieving consistent etching and well-formed openings in an inter-metal dielectric layer. The process uses a pre-coating step to modify reactor surfaces and support more uniform results.

Collaborations

Wang’s listed coworkers include Been-Hon Lin and Hung-Ju Chien. His patent is associated with Taiwan Semiconductor Manufacturing Company Ltd.

Conclusion

Chia-Cheng Wang’s patent describes a reactor pre-coating technique intended to improve etch uniformity and via/contact profiles, reflecting his contribution to semiconductor manufacturing innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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