Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Cheng Wang

Hung-Ju Chien

Been-Hon Lin

A method of manufacturing an insulating layer 30 (IMD layer) that has a uniform etch rate and forms improved via/contact opening profiles. The method forms a coating film 11 of silicon oxide over the chamber walls 22 of a CVD reactor. Next, the wafer 12 is loaded into the CVD reactor 20. A first insulating layer 30 composed of oxide preferably formed by a sub-atmospheric undoped silicon glass (SAUSG) using TEOS is formed over the semiconductor structure 12. Via/Contact Openings 32 are then etched in the insulating layer 30. The coating film 11 over the interior surfaces (e.g., reactor walls) 22 improves the etch rate uniformity of the first insulating layer 30. The first insulating layer 30 is preferably a inter metal dielectric (IMD) layer.

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Taipei, Taiwan

Chia-Cheng Wang