The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2000

Filed:

Jan. 12, 1998
Applicant:
Inventors:

Hung-Ju Chien, Hsinchu, TW;

Chia-Cheng Wang, Taipei, TW;

Been-Hon Lin, Koasuing, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
C23C / ; H01L / ;
U.S. Cl.
CPC ...
42725537 ; 427579 ; 427237 ; 427238 ; 427 99 ; 438756 ; 438435 ; 438790 ; 438905 ;
Abstract

A method of manufacturing an insulating layer 30 (IMD layer) that has a uniform etch rate and forms improved via/contact opening profiles. The method forms a coating film 11 of silicon oxide over the chamber walls 22 of a CVD reactor. Next, the wafer 12 is loaded into the CVD reactor 20. A first insulating layer 30 composed of oxide preferably formed by a sub-atmospheric undoped silicon glass (SAUSG) using TEOS is formed over the semiconductor structure 12. Via/Contact Openings 32 are then etched in the insulating layer 30. The coating film 11 over the interior surfaces (e.g., reactor walls) 22 improves the etch rate uniformity of the first insulating layer 30. The first insulating layer 30 is preferably a inter metal dielectric (IMD) layer.


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