San Jose, CA, United States of America

Chenglin Liu

This inventor holds 27 USPTO granted patents and 4 published patent applications and 1 EPO patent, primarily in Semiconductor Packaging. Top assignees: Marvell International Limited, Marvellworld Trade Ltd., Marvell Asia Pte., Ltd.. Active years: 2010-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chenglin Liu. Retrieved from https://idiyas.com/inventor/chenglin-liu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 27 

% Patents Active = 59.3


Average Co-Inventor Count = 2.3

ph-index = 6

Forward Citations = 115(Granted Patents)


Location History:

  • San Jose, CA (US) (2010 - 2017)
  • Cupertino, CA (US) (2022)

Company Filing History:


Years Active: 2010-2022

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Areas of Expertise:
Heat Sink Design
Ball Grid Array
Thermal Solutions
Semiconductor Package
Quad Flat No-Lead
Die-to-Die Wire-Bonding
Hybrid Die Package
Internal Wiring Bus
Thermal Enhanced Package
Chip on Leads
Drive Systems
27 patents (USPTO):Explore Patents

Title: Innovations of Chenglin Liu in Semiconductor Packaging

Introduction

Chenglin Liu, based in San Jose, CA, is an accomplished inventor with a remarkable portfolio of 27 patents. His work primarily focuses on advancements in semiconductor packaging, which has significant implications for the electronics manufacturing industry.

Latest Patents

Two of Chenglin Liu's latest patents exemplify his innovative contributions:

1. **Heat Sink Design for Flip Chip Ball Grid Array**

This patent describes a flip chip ball grid array (FCBGA) that includes a substrate, a cavity forming ring stiffener, an external heat sink, and a thermal interface material. The design involves a stiffener on the substrate that creates a cavity exposing the silicon chip's top. The external heat sink effectively conducts heat from the silicon chip, ensuring optimal thermal management.

2. **Dual Row Quad Flat No-Lead Semiconductor Package**

In this patent, Liu introduces a Quad Flat No-Lead package characterized by an outer row of peripheral leads and an inner row of inner peripheral leads. The design features leads with a rectangular shape having rounded corners, improving connectivity and performance in semiconductor applications.

Career Highlights

Chenglin Liu has made significant strides in his career, notably at Marvell International Limited and Marvell World Trade Ltd. His expertise in semiconductor technology has allowed him to spearhead innovations that benefit multiple sectors within the electronics landscape.

Collaborations

Throughout his career, Liu has collaborated with fellow innovators such as Shiann-Ming Liou and Chender Chen. These partnerships have bolstered his patent portfolio and contributed to advancements in semiconductor packaging techniques.

Conclusion

Chenglin Liu's contributions to the field of semiconductor packaging through his 27 patents showcase his ingenuity and commitment to innovation. His latest inventions, particularly in thermal management and device architecture, highlight the importance of advanced technologies in enhancing electronic performance. His work continues to pave the way for future advancements in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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