Marvell International Limited

Marvellworld Trade Ltd.

Marvell Asia Pte., Ltd.

Marvell International Technology Ltd

Chenglin Liu

Shiann-Ming Liou

Chender Chen

Shiann Liou

Albert M Wu

Huahung Kao

Xiaoting Chang

Sheng C Liao

A flip chip ball grid array (FCBGA) comprises a substrate, a cavity forming ring stiffener, an external heat sink, and a thermal interface material. The cavity forming ring stiffener is disposed on the substrate. The cavity forming ring stiffener has a segment which forms a cavity with the substrate, and exposes a top of the silicon chip. The external heat sink is disposed on the silicon chip and the segment of the cavity forming ring stiffener. A thermal interface material separates the segment of the cavity forming ring stiffener and the top of the silicon chip from the external heat sink and conducts heat from the silicon chip to the external heat sink.

Heat sink design for flip chip ball grid array

Some of the embodiments of the present disclosure provide a Quad Flat No-Lead package comprising: an outer row of outer peripheral leads disposed on an outer periphery of a bottom surface of the Quad Flat No-Lead package; and an inner row of inner peripheral leads disposed on an inner periphery of the bottom surface of the Quad Flat No-Lead package, wherein each of the inner peripheral leads has a substantially rectangular shape, and wherein the substantially rectangular shape has two rounded corners adjacent to the outer row of outer peripheral leads.

Dual row quad flat no-lead semiconductor package

A packaged IC having laser vias and methods for making the same. The packaged IC includes a die having bond pads thereon, wire bonds contacting the bond pads, and a substrate configured to electrically connect the wire bonds and external package connectors. The substrate includes mechanical vias through the substrate layers and laser vias in an uppermost substrate layer. Each laser via is closer to the die than the mechanical vias that do not overlap or are not covered by the die. The method includes routing traces on uppermost and lowermost layers, the traces electrically connecting a wire bonds and external package connectors, forming mechanical vias through all layers of the substrate, forming laser vias in the uppermost substrate layer, and electrically connecting each wire bond to one trace on the uppermost substrate layer.

Ball grid array package with laser vias and methods for making the same

In accordance with an embodiment, there is provided a substrate of a ball grid array package that includes a first layer including reinforcement fibers. The reinforcement fibers reinforce the first layer such that the first layer has a higher tensile strength relative to a layer in the ball grid array package that is free of reinforcement fibers. In an embodiment, the substrate comprises a second layer disposed adjacent to the first layer with the second layer being free of reinforcement fibers. In an embodiment, the substrate also includes a through hole penetrating each of the first layer and the second layer. The through hole penetrates each of the first layer and the second layer based on each of the first layer and the second layer having been drilled in accordance with a mechanical drilling process.

Ball grid array package substrate with through holes and method of forming same

Semiconductor packages and associated techniques are described. A described semiconductor package includes a lead frame; a first wire bond; a second wire bond; a first voltage source to provide a first voltage; a second voltage source to provide a second voltage; a first die pad coupled with the first voltage source via the first wire bond; a second die pad coupled with the second voltage source via the second wire bond; a first die disposed on the first die pad; a second die disposed on the second die pad; and an encapsulant. The first die pad and the second die pad can be electrically isolated from each other such that the first die pad is maintainable at a first potential associated with the first voltage source and the second die pad is maintainable at a second potential associated with the second voltage source.

Semiconductor package

Embodiments provide a method of fabricating a semiconductor package, the method comprising forming a leadframe, wherein the leadframe includes an inner lead, and wherein a bottom surface of the inner lead comprises a first section and a second section; depositing an oxidation resistant material on the first section of the bottom surface of the inner lead; and forming an oxidation layer on the second section of the bottom surface of the inner lead, wherein the oxidation resistant material deposited on the first section of the bottom surface of the inner lead prevents the oxidation layer from forming on the first section of the bottom surface of the inner lead.

Formation of package pins in semiconductor packaging

A packaged IC having laser vias and methods for making the same. The packaged IC includes a die having bond pads thereon, wire bonds contacting the bond pads, and a substrate configured to electrically connect the wire bonds and external package connectors. The substrate includes mechanical vias through the substrate layers and laser vias in an uppermost substrate layer. Each laser via is closer to the die than the mechanical vias that do not overlap or are not covered by the die. The method includes routing traces on uppermost and lowermost layers, the traces electrically connecting wire bonds and external package connectors, forming mechanical vias through all layers of the substrate, forming laser vias in the uppermost substrate layer, and electrically connecting each wire bond to one trace on the uppermost substrate layer.

Systems, methods, and other embodiments associated with an etched hybrid die package are described. According to one embodiment, a method includes electrically connecting a semiconductor die to at least one of a plurality of primary leads and at least one feature. The method includes applying an encapsulant material to a lead-frame that includes the plurality of primary leads to form a package body. Portions of the primary leads protrude from the package body and portions of the at least one feature are exposed within the package body. The method includes chemically etching a die pad exposed within the package body to form and electrically isolate the at least one feature from the die pad. Chemically etching includes fully etching the at least one feature from the die pad.

Etched hybrid die package

A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector.

Thermal enhanced package

A system including a printed circuit board having a plurality of vias, a first integrated circuit mounted on a first surface of the printed circuit board, and a casing mounted on a second surface of the printed circuit board. The first surface of the printed circuit board is opposite to the second surface of the printed circuit board. Each of the plurality of vias has (i) a first end extending to the first surface of the printed circuit board and (ii) a second end extending to the second surface of the printed circuit board. The first integrated circuit is in thermal contact with the first ends of the plurality of vias. The casing is in thermal contact with the second ends of the plurality of vias.

Thermal solution for drive systems such as hard disk drives and digital versatile discs

Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated circuit chip onto the bonding fingers may reduce the pin-out count by allowing multiple integrated circuit chips to be interconnected within the same microelectronic package. Other embodiments may be described and claimed.

Chip on leads

Embodiments of the present disclosure describe semiconductor device packaging techniques and devices that incorporate a heat spreader into the insulating material of a packaged semiconductor device. In one embodiment, a device comprising a semiconductor device is coupled to a substrate, and insulating material covers (i) a portion of the semiconductor device and (ii) a portion of the substrate. The device also comprises a heat spreader embedded in the insulating material and the heat spreader is isolated from the substrate at least in part by the insulating material.

Placing heat sink into packaging by strip formation assembly

An embodiment includes a method that includes encapsulating a die and at least a portion of a lead-frame in a mold to form a package body. At least one primary lead attached to the lead-frame extends from the package body. The method includes etching a feature to within a threshold in an exposed die pad. The exposed die pad comprises a first surface that is prepared for etching and a second surface opposite to the first surface and attached to the die. The method includes positioning the die within a footprint of the exposed die pad, connecting the die to at least one primary lead, and connecting the feature to the die.

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San Jose, CA, United States of America

Chenglin Liu