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For the Inventor, By the Inventor

Hsinchu, Taiwan

Cheng-Tsung Ni

USPTO Granted Patents = 13

Average Co-Inventor Count = 1.7

ph-index = 6

Forward Citations = 148(Granted Patents)


Location History:

  • Hsinchu Hsien, TW (2003)
  • Hsinchu, TW (1998 - 2005)

Company Filing History:

goldMedal13 out of 442 
 
Mosel Vitelic Corporation
 patents

Years Active: 1998-2005

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13 patents (USPTO):Explore Patents
1. 6888197 - Power metal oxide semiconductor field effect transistor layout (2005-05-03),
2. 6821913 - Method for forming dual oxide layers at bottom of trench (2004-11-23),
3. 6784115 - Method of simultaneously implementing differential gate oxide thickness using fluorine bearing impurities (2004-08-31),
4. 6660592 - Fabricating a DMOS transistor (2003-12-09),
5. 6657263 - MOS transistors having dual gates and self-aligned interconnect contact windows (2003-12-02),
6. 6563166 - Flash cell device (2003-05-13),
7. 6284578 - MOS transistors having dual gates and self-aligned interconnect contact windows (2001-09-04),
8. 6228729 - MOS transistors having raised source and drain and interconnects (2001-05-08),
9. 6150244 - Method for fabricating MOS transistor having raised source and drain (2000-11-21),
10. 6127699 - Method for fabricating MOSFET having increased effective gate length (2000-10-03),
11. 6008106 - Micro-trench oxidation by using rough oxide mask for field isolation (1999-12-28),
12. 5972754 - Method for fabricating MOSFET having increased effective gate length (1999-10-26),
13. 5804493 - Method for preventing substrate damage during semiconductor fabrication (1998-09-08),

Title: Innovations of Cheng-Tsung Ni

Introduction

Cheng-Tsung Ni is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 13 patents. His work focuses on improving the efficiency and functionality of power metal oxide semiconductor devices.

Latest Patents

One of his latest patents is titled "Power metal oxide semiconductor field effect transistor layout." This invention describes a power MOSFET layout that includes a substrate and multiple cells. Each cell features a base portion, protruding portions, and photo-resist regions, all geometrically configured to define a closed cell boundary. The cells are arranged in a matrix format, ensuring no overlapping occurs among them. Another notable patent is the "Method for forming dual oxide layers at the bottom of trench." This method outlines an improved technique for creating dual oxide layers within a trench of a substrate, enhancing the overall performance of semiconductor devices.

Career Highlights

Cheng-Tsung Ni is currently employed at Mosel Vitelic Corporation, where he continues to innovate in the semiconductor industry. His expertise in semiconductor fabrication processes has positioned him as a key figure in his field.

Collaborations

He has collaborated with notable coworkers, including Chih-hsun Chu and Chiao-Shun Chuang, contributing to various projects that advance semiconductor technology.

Conclusion

Cheng-Tsung Ni's innovative work in semiconductor technology has led to significant advancements in the field. His patents reflect a commitment to enhancing the efficiency and functionality of electronic devices.

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