Mos transistors having raised source and drain and interconnects

Abstract

A process for fabricating a semiconductor device comprising a gate electrode, a raised source, a raised drain and an interconnect inlaid into an isolation region. A semiconductor device is fabricated by a process comprising the following steps: forming sequentially a first dielectric layer and a first conductor layer on the substrate; forming one or more inset isolation regions in the substrate; filling each inset isolation region with an isolation layer; forming a second dielectric layer on top of the first conductor layer and the isolation layers; forming simultaneously a first and a second trench; forming a plurality of cavities at the bottom of the first trench; filling each cavity with a second conductor layer; forming a plurality of dielectric sidewalls and a dielectric bottom layer in the first trench; forming the gate electrode and the interconnect by filling the first and second trenches with a third conductor layer; doping the first conductor layer with dopants; and forming the raised source and the raised drain by driving the dopants into the surface region of the substrate.