Mosel Vitelic Corporation

Cheng-Tsung Ni

Chih-hsun Chu

Chiao-Shun Chuang

Mao-Song Tseng

Chien-Ping Chang

Chih-Sheng Chang

Chih-Hsien Wang

Tuby Tu

Jacson Liu

Jen-Te Chen

Chen Kuang-Chao

Hudy-Jong Wu

Minn-Horng Juang

A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions. Each of the cells is geometrically configured with the base portion and the plurality of protruding portions defining a closed cell boundary enclosing each of said cells. The cells are formed over the substrate, and the closed cell boundaries of the cells are arranged regularly with each other with no overlapping among the cells. The base portions are disposed in a matrix arrangement having rows and columns. The base portions are oriented from end to end in a direction of the columns and the protruding portions extend from the base portions along a direction of the rows. The photo-resist regions cover the base portions on the same column. None of the protruding portions are disposed between the base portions on the same column. The cells are doped with N type dopants by using the photo-resist regions as masks.

Power metal oxide semiconductor field effect transistor layout

Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defining the mask oxide layer to form a patterned mask oxide layer and exposing a partial surface of the substrate to form a window; and using the patterned mask oxide layer as an etching mask to form the trench in the window. A first oxide layer is formed on the sidewall and the bottom of the trench of the substrate. A photoresist layer is formed on the substrate, filling the trench of the substrate. The method further comprises partially etching back the photoresist layer to leave a remaining photoresist layer in the trench. The height of the remaining photoresist layer is lower than the depth of the trench. A curing treatment of the remaining photoresist layer is performed after the partial etching. The patterned mask oxide layer and a portion of the first oxide layer are removed to leave a remaining first oxide layer at the bottom of the trench. The remaining photoresist layer is removed. A second oxide layer is formed on the substrate covering at least the remaining first oxide layer to form the dual oxide layers at the bottom of the trench.

Method for forming dual oxide layers at bottom of trench

Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer ( ) that is thin in some regions, such as the cell region, and thicker in other regions ( ), such as the periphery region. The method simultaneously provides a gate oxide layer with two or more thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to a specific embodiment of the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor ROM device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor ROM device.

Method of simultaneously implementing differential gate oxide thickness using fluorine bearing impurities

Embodiment of the present invention are directed to improving the performance of a DMOS transistor. A method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a gate oxide and a trenched gate, and implanting first conductive dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form a first doping region. An insulating layer is deposited over the semiconductor substrate; and selectively etching the insulating layer to form a source contact window over a central portion of the first doping region and to leave an insulator structure above the trenched gate. The source contact window of the insulating layer has an enlarged top portion which is larger in size than a bottom portion of the source contact window closer to the first doping region than the enlarged top portion. The enlarged top portion is typically bowl-shaped. Second conductive dopants are implanted through the source contact window to form a second doping region in the central portion of the first doping region.

Fabricating a DMOS transistor

A method of fabricating an IC device on a substrate comprising MOS transistors and other IC components. Each of the transistors of the IC device comprises a raised source electrode, a raised drain electrode, dual gate electrodes and self-aligned interconnect contact windows, and is connected to other transistors and other IC components through interconnects formed on top of such self-aligned contact windows.

MOS transistors having dual gates and self-aligned interconnect contact windows

A memory device includes a first memory cell and a second memory cell both controlled by a common control gate. The device includes: a substrate; first and second stacks each including an insulating layer formed over the substrate, a first conductive layer formed over the insulating layer and providing a select gate, and a first dielectric layer formed over the first conductive layer, each of the stacks also including an inner sidewall and an outer sidewall, the. stacks being separated by a common area of the substrate, the inner and outer sidewalls of the stacks being coated with a second dielectric layer; first and second spacers formed adjacent the inner sidewalls of the first and second stacks respectively, the first and second spacers being separated by a medial portion of the common source area of the substrate, each of the spacers. including a tunnel oxide layer disposed over the substrate, and a second conductive layer disposed over the tunnel oxide layer and providing a floating gate; first and second drain regions formed in the substrate proximate the outer sidewalls of the first and second stacks; a common source region formed beneath the common source area; a third dielectric layer disposed over the first and second spacers, and the first and second stacks; and a third conductive layer, disposed over inner portions of the first and second select gate stacks, and forming the common control gate.

Flash cell device

A process for fabricating a semiconductor device comprising a gate electrode, a raised source, a raised drain and an interconnect inlaid into an isolation region. A semiconductor device is fabricated by a process comprising the following steps: forming sequentially a first dielectric layer and a first conductor layer on the substrate; forming one or more inset isolation regions in the substrate; filling each inset isolation region with an isolation layer; forming a second dielectric layer on top of the first conductor layer and the isolation layers; forming simultaneously a first and a second trench; forming a plurality of cavities at the bottom of the first trench; filling each cavity with a second conductor layer; forming a plurality of dielectric sidewalls and a dielectric bottom layer in the first trench; forming the gate electrode and the interconnect by filling the first and second trenches with a third conductor layer; doping the first conductor layer with dopants; and forming the raised source and the raised drain by driving the dopants into the surface region of the substrate.

MOS transistors having raised source and drain and interconnects

A process for fabricating a semiconductor device comprising a raised source and drain. A semiconductor device is fabricated by a process comprising the following steps: forming active regions separated by isolation regions; forming at each active region a gate electrode structure; depositing a first dielectric layer and a second dielectric layer; removing the top portion of the second dielectric layer to expose the portion of the first dielectric layer that covers the gate electrode structure; forming on the substrate a patterned resist layer to mask portions of the second dielectric layer; forming trenches next to the gate electrode structure by removing the unmasked portions of the second dielectric layer; filling the trenches with a conductor; doping the conductor with dopants; and driving the dopants into the substrate to form the raised source and drain.

Method for fabricating MOS transistor having raised source and drain

A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming a lightly doped region in each active area; forming a heavily doped p-Si (or a-Si) layer; depositing and patterning several dielectric layers to form a gate area surrounded by vertical spacers; forming a groove in the gate area and the substrate; forming a gate oxide layer in the groove and driving dopants in the doped p-Si (or a-Si) layer into the substrate to form the source and the drain; and forming a gate electrode in the groove.

Method for fabricating MOSFET having increased effective gate length

A method of forming isolation region of an integrated circuit by using rough oxide mask is described. First, a layer of first dielectric is formed on the surface of a silicon substrate. The first dielectric layer is then patterned to define active device region and isolation region. Next, a very thin layer of silicon dioxide is formed over the silicon substrate surface, followed by depositing a layer of rough oxide with proper grain size overlaying the silicon dioxide layer. By using rough oxide grains as an etching mask, the silicon dioxide layer and the silicon substrate underneath are spontaneously etched to form multiple trenches in the isolation region. Next, the rough oxide grains and silicon dioxide layers are stripped. Then, filed oxidation is performed to complete the field oxide isolation formation.

Micro-trench oxidation by using rough oxide mask for field isolation

A method for preventing substrate damage during semiconductor fabrication, comprising, forming a pad oxide layer on the substrate, depositing a polysilicon buffer layer on the pad oxide layer, ion-implanting fluorine into the polysilicon buffer layer, depositing a silicon nitride layer on the polysilicon buffer layer, defining an active region in the substrate, forming a local oxide layer beside the surface of the active region, removing the silicon nitride layer, removing the polysilicon buffer layer by dry etching, and etching the pad oxide layer to expose the substrate surface of active region.

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Hsinchu, Taiwan

Cheng-Tsung Ni