The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2004
Filed:
Dec. 18, 1998
Cheng-Tsung Ni, Hsinchu, TW;
Jacson Liu, Hsinchu, TW;
Chih-Sheng Chang, Hsinchu, TW;
Hudy-Jong Wu, Hsinchu, TW;
Mosel Vitelic, Inc., Hsinchu, TW;
Abstract
Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer ( ) that is thin in some regions, such as the cell region, and thicker in other regions ( ), such as the periphery region. The method simultaneously provides a gate oxide layer with two or more thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to a specific embodiment of the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor ROM device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor ROM device.