Flash cell device

Abstract

A memory device includes a first memory cell and a second memory cell both controlled by a common control gate. The device includes: a substrate; first and second stacks each including an insulating layer formed over the substrate, a first conductive layer formed over the insulating layer and providing a select gate, and a first dielectric layer formed over the first conductive layer, each of the stacks also including an inner sidewall and an outer sidewall, the. stacks being separated by a common area of the substrate, the inner and outer sidewalls of the stacks being coated with a second dielectric layer; first and second spacers formed adjacent the inner sidewalls of the first and second stacks respectively, the first and second spacers being separated by a medial portion of the common source area of the substrate, each of the spacers. including a tunnel oxide layer disposed over the substrate, and a second conductive layer disposed over the tunnel oxide layer and providing a floating gate; first and second drain regions formed in the substrate proximate the outer sidewalls of the first and second stacks; a common source region formed beneath the common source area; a third dielectric layer disposed over the first and second spacers, and the first and second stacks; and a third conductive layer, disposed over inner portions of the first and second select gate stacks, and forming the common control gate.