Che-Liang Chung

This inventor holds 6 USPTO granted patents and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2017-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Che-Liang Chung. Retrieved from https://idiyas.com/inventor/che-liang-chung

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6 (Patent Applications = 1)

% Patents Active = 83.3

Average Co-Inventor Count = 4.5

ph-index = 1

Forward Citations = 17(Granted Patents)

Location History:

Taoyuan, TW (2017 - 2024)
Hsinchu, TW (2024)

Company Filing History:

6 out of 42,810

Taiwan Semiconductor Manufacturing Comp. Ltd.

patents

Years Active: 2017-2024

Loading Chart...

6 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12068196 - Forming gate line-end of semiconductor structures with improved metal gate height (2024-08-20),

2. 11951587 - Zone-based CMP target control (2024-04-09),

3. 10943822 - Forming gate line-end of semiconductor structures (2021-03-09),

4. 10164053 - Semiconductor device and method (2018-12-25),

5. 10160088 - Advanced polishing system (2018-12-25),

6. 9802292 - Advanced polishing system (2017-10-31),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: