Tainan, Taiwan

Chao-Hsien Huang

This inventor holds 22 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Technology. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2018-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chao-Hsien Huang. Retrieved from https://idiyas.com/inventor/chao-hsien-huang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 22 

% Patents Active = 100.0

Average Co-Inventor Count = 4.8

ph-index = 3

Forward Citations = 25(Granted Patents)


Location History:

  • Hsinchu, TW (2019 - 2023)
  • Tainan, TW (2018 - 2024)

Company Filing History:


Years Active: 2018-2025

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Areas of Expertise:
Semiconductor Device
FinFET Fabrication
Air Spacers
Transistors
Interconnect Structure
Conductive Vias
Loading Effect
CMOS Device
Device Arrangement
Manufacturing Method
22 patents (USPTO):Explore Patents

Title: Innovations of Chao-Hsien Huang in Semiconductor Technology

Introduction

Chao-Hsien Huang, a distinguished inventor based in Tainan, Taiwan, has made significant contributions to semiconductor technology, holding a remarkable 19 patents to his name. His innovative work primarily focuses on enhancing the performance and efficiency of semiconductor devices, demonstrating his expertise in this rapidly evolving field.

Latest Patents

Huang's latest patents reflect his commitment to advancing semiconductor structures. One notable invention is the patent for a **semiconductor device with reduced loading effect**. This patent describes a method that encompasses depositing a dielectric layer on a substrate followed by a patterning layer. The process involves a first etching technique that creates regions with varying pattern densities, ultimately leading to the formation of fin structures that significantly improve device performance.

Another recent innovation by Huang is the **method for FinFET fabrication and structure thereof**. This patent outlines a semiconductor device that features a substrate with a protruding semiconductor fin and an isolation layer above it. The design includes a dielectric fin embedded in the isolation layer, further enhancing the structural integrity and performance of the semiconductor device.

Career Highlights

Chao-Hsien Huang is associated with the Taiwan Semiconductor Manufacturing Company, Ltd., a leading player in the semiconductor industry. His career milestones are marked by his inventive prowess and his continuous quest for technological advancement in semiconductor manufacturing processes.

Collaborations

Throughout his career, Huang has collaborated with notable colleagues such as Li-Te S Lin and Jung-Hao Chang. These partnerships have fostered an environment of innovation, allowing them to develop groundbreaking technologies that have contributed to the semiconductor industry's evolution.

Conclusion

Chao-Hsien Huang's contributions to semiconductor technology through his numerous patents showcase his role as a pivotal figure in the field. His latest innovations not only improve semiconductor performance but also set the stage for future advancements in electronic devices. Huang's work exemplifies the spirit of innovation that drives the technology sector forward.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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