San Jose, CA, United States of America

Chao-Chun Lo

This inventor holds 6 USPTO granted patents and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2022-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chao-Chun Lo. Retrieved from https://idiyas.com/inventor/chao-chun-lo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6 

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 2

Forward Citations = 11(Granted Patents)


Location History:

  • San Jose, CA (US) (2022 - 2023)
  • Hsinchu, TW (2022 - 2023)

Company Filing History:


Years Active: 2022-2024

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6 patents (USPTO):Explore Patents

Title: Chao-Chun Lo: Innovator in Semiconductor Design

Introduction

Chao-Chun Lo is a prominent inventor based in San Jose, CA, known for his significant contributions to semiconductor design. With a total of 6 patents, he has made remarkable advancements in the field, particularly in generating synthesizable netlists and migrating ASIC designs across different semiconductor fabrication processes.

Latest Patents

Chao-Chun Lo's latest patents include innovative systems and methods for generating synthesizable netlists from register transfer level (RTL) designs. These methods aid in semiconductor device design by providing RTL design information that corresponds to portions of a semiconductor device. His work involves a configuration tracer that generates behavior information associated with the RTL design, and a register compiler that compiles semiconductor devices based on various technologies and power, performance, and area (PPA) information. Additionally, he has developed an apparatus and method for mapping foundational components during design porting from one process technology to another. This method includes parsing gate-level netlists and generating target gate-level netlists that describe ASIC designs in terms of equivalent target standard cells.

Career Highlights

Chao-Chun Lo is currently employed at Taiwan Semiconductor Manufacturing Company Limited, where he continues to push the boundaries of semiconductor technology. His expertise in the field has led to numerous innovations that enhance the efficiency and effectiveness of semiconductor device design.

Collaborations

Throughout his career, Chao-Chun Lo has collaborated with notable colleagues, including Boh-Yi Huang and Chih-yuan Stephen Yu. These collaborations have contributed to the advancement of semiconductor technologies and the successful implementation of innovative designs.

Conclusion

Chao-Chun Lo's contributions to semiconductor design through his patents and collaborative efforts highlight his role as a key innovator in the industry. His work continues to influence the future of semiconductor technology and design methodologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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