The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2022
Filed:
Apr. 23, 2021
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Chih-yuan Stephen Yu, San Jose, CA (US);
Boh-Yi Huang, San Jose, CA (US);
Chao-Chun Lo, San Jose, CA (US);
Xiang Guo, San Jose, CA (US);
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.