The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2024

Filed:

Jul. 10, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Boh-Yi Huang, San Jose, CA (US);

Chao-Chun Lo, San Jose, CA (US);

Chih-yuan Stephen Yu, San Jose, CA (US);

Tze-Chiang Huang, Saratoga, CA (US);

Chen-jih Lui, Union City, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 8/41 (2018.01); G06F 115/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 8/41 (2013.01); G06F 2115/02 (2020.01);
Abstract

Methods, systems, and computer program products are described for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design. These netlists provide RTL design information corresponding to a portion of a semiconductor device. A configuration tracer generates behavior information associated with the RTL design. A register compiler compiles a set of semiconductor devices based on one or more technologies and power, performance, and area (PPA) information related to the semiconductor device. Semiconductor devices generated by the register compiler that meet predefined power, performance, and area conditions are identified. Structural information for aligning the input/output ports of the semiconductor device is generated. A set of one or more synthesizable semiconductor device configurations is created based on user defined parameters such that one of the synthesizable semiconductor device designs may by selected to generate a design netlist with structure-synthesizable input/output boundary compatible semiconductor device modules.


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