San Jose, CA, United States of America

Byungha Joo

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignee: Intel Corporation. Active years: 2003-2009.

USPTO Granted Patents = 2 

% Patents Active = 50.0

Average Co-Inventor Count = 1.7

ph-index = 1

Forward Citations = 4(Granted Patents)


Company Filing History:


Years Active: 2003-2009

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2 patents (USPTO):Explore Patents

Title: Byungha Joo: Innovator in Integrated Circuit Design

Introduction

Byungha Joo is a notable inventor based in San Jose, CA, who has made significant contributions to the field of integrated circuit design. With a focus on enhancing circuit efficiency and reducing power consumption, Joo has been awarded 2 patents that showcase his innovative approach to technology.

Latest Patents

Joo's latest patents include "Shallow trench avoidance in integrated circuits," which addresses the bridging of diffusion regions across cell boundaries. This innovation reduces shallow trench isolation and minimizes nitride passivation thickness variation. Another significant patent is the "Low power dual trip point input buffer circuit," which presents a method for decreasing power consumption in circuits that utilize inverters with resistive load designs. This circuit operates in a CMOS configuration, effectively driving both the load and logic networks with the input signal.

Career Highlights

Byungha Joo is currently employed at Intel Corporation, where he continues to push the boundaries of integrated circuit technology. His work is instrumental in developing more efficient and effective electronic components.

Collaborations

Joo collaborates with talented colleagues, including Jeffrey B. Davis and Duc G. Nguyen, who contribute to the innovative environment at Intel Corporation.

Conclusion

Byungha Joo's contributions to integrated circuit design through his patents reflect his commitment to innovation and efficiency in technology. His work continues to influence the field and drive advancements in electronic design.

Profile summary based on public USPTO records.
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