Intel Corporation

Byungha Joo

Jeffrey B Davis

Rajashri Doddamani

Darshana Surti

Eva Yim

Duc G Nguyen

Diffusion regions in a standard cell design are bridged across cell boundaries. Shallow trench isolation is reduced and nitride passivation thickness variation is reduced.

Shallow trench avoidance in integrated circuits

A method and system for reducing the power consumption in a class of circuits utilizing inverters which rely upon a resistive load design such as pseudo NMOS and/or pseudo PMOS. In particular, rather than utilizing the load network to provide a resistive load, which imposes static dissipation, the load network is driven by the input signal along with the logic network. The circuit is then configured to function in a CMOS configuration by driving both the load and logic networks with the input signal.

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San Jose, CA, United States of America

Byungha Joo