The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2003
Filed:
Dec. 19, 2001
Applicant:
Inventor:
Byungha Joo, San Jose, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 ;
U.S. Cl.
CPC ...
H03K 3/037 ;
Abstract
A method and system for reducing the power consumption in a class of circuits utilizing inverters which rely upon a resistive load design such as pseudo NMOS and/or pseudo PMOS. In particular, rather than utilizing the load network to provide a resistive load, which imposes static dissipation, the load network is driven by the input signal along with the logic network. The circuit is then configured to function in a CMOS configuration by driving both the load and logic networks with the input signal.