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Santa Clara, CA, United States of America

Brent Alan Fairbanks

USPTO Granted Patents = 9

Average Co-Inventor Count = 1.7

ph-index = 7

Forward Citations = 575(Granted Patents)

Location History:

Santa Clara, CA (US) (1999 - 2008)
San Jose, CA (US) (2013)

Company Filing History:

Altera Corporation

Years Active: 1999-2013

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9 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8488729 - Deskew across high speed data lanes (2013-07-16),

2. 7398483 - Design verification method for programmable logic design (2008-07-08),

3. 7111265 - I/O pin placement for a programmable logic device (2006-09-19),

4. 6601221 - Design verification method for programmable logic design (2003-07-29),

5. 6298319 - Incremental compilation of electronic design for work group (2001-10-02),

6. 6182020 - Design verification method for programmable logic design (2001-01-30),

7. 6043676 - Wide exclusive or and wide-input and for PLDS (2000-03-28),

8. 6026226 - Local compilation in context within a design hierarchy (2000-02-15),

9. 5983277 - Work group computing for electronic design automation (1999-11-09),

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